4H-SiC Planar MOSFET (650V)

1. Abstract

This application note presents the design and simulation of a conventional 4H-SiC planar metal-oxide-semiconductor field-effect-transistor (MOSFET) rated at 650 V, using Aquarius TCAD tool. This example covers the description of the device active area, including structural dimensions, contact definitions, doping profiles and the meshing strategy. It then describes the setup for simulating static performance, including transfer (V_GS – I_DS), output (V_DS – I_DS), and off-state characteristics.

2. Introduction

4H-SiC technology is vital for modern power electronics, offering superior performance over conventional Si devices. In the 650 V class, key applications include electric and hybrid vehicles. Device design focuses on reducing on-state losses while maintaining a desired blocking voltage and minimising the gate-oxide electric field (EF) to ensure long-term reliability, a critical issue in 4H-SiC MOS devices [1-3]. The Aquarius TCAD tool enables exploration of design trade-offs by accurately modelling device physics to support the fabrication process.

3. Device Structure

The 650 V MOSFET model discussed in this report is based on the device parameters reported in [3]. Fig. 1. shows the half-cell MOSFET structure with its key parameters (also summarised in Table 1).

Fig. 1. Half-cell structure

In this report, two design geometries (G1 and G2) will be investigated, each featuring a different half-cell JFET opening (W_JFET) of 0.4 µm and 0.6 µm, respectively. In both designs, the P+ region is 0.6 µm in depth and 1.5 µm wide (half-cell). The N+ region opening is 0.6 µm and 0.2 µm deep. Note, that the JFET region has a constant 4E+16 cm^-3 doping concentration, whereas N+, P+, P-Channel and P-body regions are modelled using Gaussian profiles (discussed in more detail in the next section).

3.1. Geometry

Table 1(a): Model G1 and G2 parameters (Half-Cell)

Parameter	Symbol	G1	G2	Unit
½ Cell width	WCELL	3	3.2	µm
JFET width	WJFET	0.4	0.6	µm
JFET depth	LJFET	0.7	0.7	µm
Substrate thickness	LSUB	2	2	µm
Drift thickness	LDRIFT	6.3	6.3	µm
Channel length	LCH	0.5	0.5	µm
Source contact width	WSOURCE	1.7	1.7	µm

3.2. Regions

Table 1(b): Region Properties

Region	Material	Donor Doping	Acceptor Doping
Oxide	Oxide	0.0	0.0
N- JFET	SiC	$4\times10^{16}$	0.0
N- DRIFT	SiC	$2\times10^{16}$	0.0
N+ SUBSTRATE	SiC	$2\times10^{18}$	0.0

3.3. Doping Windows

Table 1(c): Doping Properties

Doping Window	Type	Function	Peak Doping	Doping at Bottom
P+	Acceptor	Gaussian	$1\times10^{19}$	$4\times10^{16}$
N+	Donor	Gaussian	$1\times10^{19}$	$4\times10^{16}$
P-CH	Acceptor	Gaussian	$3\times10^{17}$	$7\times10^{16}$
P-Body	Acceptor	Gaussian	$2\times10^{18}$	$4\times10^{16}$

4. Device Meshing and Doping Concentration Profiles

4.1. Mesh Construction Grid

The device mesh is a critical aspect of the accuracy and numerical stability of the calculation/solution. The first step is to define a mesh construction grid, followed by applying the global refinements. It is important to refine regions around the p–n junctions, the channel area (e.g. around the gate-oxide/4H-SiC interface) and other regions where the potential and carrier concentration change substantially. An example of the mesh grid for design G1 is shown in Fig. 2.

Fig. 2. The Mesh Grid. (a) Full-Device, (b) Active Region, (c) Drift/Substrate Interface.

The mesh density is increased in the active regions (P+, N+ etc.) with additional refinement in the JFET region (see Fig. 2(b).), where the current flow curves downward. Further mesh refinement is applied at the gate-oxide and interface region, as those regions are critical for channel formation.

Additional refinement is introduced at the drift–substrate interface, (see Fig. 2(c).), to accurately capture the electric field distribution during the off-state, where the field extends through the drift layer and changes rapidly at the drift-substrate interface.

4.2. Mesh Refinement Settings

The meshed device without and with refinement is shown in Fig. 3(a). and Fig. 3(b)., where the refined option produces a higher quality mesh in critical regions.

Fig. 3(a). Meshed device without refinement.

Fig. 3(b). Meshed device with refinement.

The refinement parameters are listed in Table 2. The number of iterations controls how many times the refinement algorithm is applied. Distance from junctions defines the range on each side of the p–n junction, where the mesh is refined.

Table 2: Mesh Refinement Settings

Setting	Value
Number of Iterations	3
Refinement Variable	Distance from Junction
Distance	0.1 μm
Reduction Factor	0.5

tip

For more detailed information on the mesh refinement settings, click here.

4.3. Doping Concentration Profiles

Using the Results Visualiser tool, the net doping concentration (N_A - N_D) can be obtained. Cut line profiles through the P+ (C1: x = 0.3), N+ (C2: x = 1.7), P-Channel (C3: x = 2.3) and N-JFET (C4: x = 2.9) regions for Model G1 are shown in Fig. 4.

Fig. 4(a). Cut line schematic.

Fig. 4(b). Net doping distribution.

Fig. 4(c). Absolute net doping Profile through C1, C2, C3 and C4.

Fig. 4(d). Absolute net doping Profile through C1, C2, C3 and C4, zoomed around the active region of the device.

Both the P+ (C1) and N+ (C2) regions are heavily doped to a peak concentration of $1\times10^{19}$ cm^-3 to establish low-resistance Ohmic contacts. The channel region, P-CH (C3), located at the gate-oxide/4H-SiC interface, is doped to $3\times10^{17}$ cm^-3 to achieve a required threshold voltage (calibration details are discussed in the next section). The P-body (C2 & C3) features a peak doping concentration of $2\times10^{18}$ cm^-3 (retrograde doping profile) [3], which prevents reach-through to the N+ source during the off-state and ensures reliable blocking capability.

The static characteristics of the MOSFET model based on these design parameters will be discussed in the following sections.

5. Physical Models

To perform the simulations, appropriate physical models must first be selected. In this example, the default SiC material parameters are used. For advanced calibration, these parameters can be modified or externally imported. The selected physics models are shown in Fig. 5.

Fig. 5. Physical Models. From left to right: (a) General, (b) Mobility, (c) Recombination, (d) Other.

For on-state simulations of the SiC MOSFET, the mobility models includes temperature (Lattice) scattering, ionised-impurity scattering (Doping), and high-field velocity saturation (High-Field) to capture dominant mobility scattering effects. For simplicity, interface mobility has been omitted. The high-field mobility is calculated using the element-averaged electric field (E Field) option for numerical stability and convergence. The recombination models are SRH and Auger. Carrier transport is modelled with classical drift–diffusion and Fermi–Dirac statistics. Fermi–Dirac statistics is necessary to accurately model the carrier density-Fermi level relationship in the heavily doped regions.

note

Impact ionisation is not shown as enabled here however it is recommended that this should be used for the off-state (breakdown) simulations.

6. Simulation Setup

All simulations are performed in the Circuit Editor by constructing a circuit with a device and a voltage or current source and connecting them to the appropriate device terminals (see Fig. 6).

Fig. 6. The circuit used to simulate the MOSFET current–voltage (CV) on-state (Transfer and Output) characteristics and the device properties window.

The first step is in creating a simulation circuit is to import the device (.sdm) that was generated in the Device Editor. Once imported, double‑clicking on the device component allows you to adjust the terminal layout and define the scaling factor. Next add a DC voltage source (S1) and connect it to gate, source and ground and then add a second voltage source and connect it to the drain.

6.1. Scaling Factor

The scaling factor corresponds to the device depth in the z‑direction (d). In this simulation, we set the device’s active area (A) to 1 cm², so that the resulting current directly represents a current density (A/cm²). To achieve this, we calculate the required depth d such that the cross‑sectional area equals 1 cm², using

$$d = \dfrac{A}{W_{\text{MOSFET}}}$$

Thus the scaling factor for G1 (W_MOSFET = 3.0 µm) d = 3333.3 cm, and for G2 (W_MOSFET = 3.2 µm) d = 3125 cm

6.2. Solver Options

As the final step before simulating the on-state and off-state characteristics of the MOSFET, appropriate solver options must be selected. To improve convergence, the solver parameters modified from their default values in the ‘non-linear algebra settings’ are summarised in Table 3.

Table 3: Solver Options - Non-Linear algebra Settings changed from Default

Setting	Value
Voltage Tolerance	0.01 V
Max Update Increases	6
Max No Back Track Steps	15
Back Track Decrement Factor	3

In the next sub-sections on-state and off-state simulations will be described in detail.

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6.3. On-State Characteristics

The goal is to simulate the transfer (I_DS - V_GS) and output (I_DS - V_DS) characteristics. In this example, the transfer characteristics are simulated with V_GS swept from 0 to 15 V at a fixed V_DS of 2 V. The output characteristics are simulated at V_GS values of 15 V and 20 V with V_DS swept from 0 to 2 V. To ensure stable convergence, the solution is divided into two steps shown in Table 4.

Table 4: Transfer and Output Simulation Steps

Test Type	Procedure
Transfer	Step 1: Ramp-up VDS to 2 V, while VGS=0V. Step 2: Using the solution from Step 1 as the initial condition, sweep VGS from 0 V to 15
Output	Step 1: Ramp-up VGS to 15 V or 20 V, while VDS=0V. Step 2: Using the solution from Step 1 as the initial condition, sweep VDS from 0 V to 2 V.

To ensure accuracy and stable convergence, using a minimum voltage step of 0.1 V in the DC sources is recommended and will be used in all simulations in this example.

note

Make sure to set the appropriate initial conditions and use the corresponding voltage source values. Note that the simulation will not start if the net-list does not match the defined initial conditions (adding extra components or mismatched sources is not allowed).

For more detail using a previous simulation as a starting point see Start from an Initial Condition.

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6.4. Off-State Characteristics

To simulate blocking and breakdown conditions, the impact ionisation model should be enabled (see Fig. 5(c).). It is recommended to use edge-based calculation for the impact ionisation to improve the accuracy of the results. The parameter values used can be seen in Table 5 below.

Table 5. Chynoweth model parameters.

Variable	Value
AV_ALPH_P	$6.216\times10^{6}$
AV_BETA_P	$1.68\times10^{7}$
AV_ALPH_N	$1.992\times10^{6}$
AV_BETA_N	$1.527\times10^{7}$

The off-state can be simulated using a similar circuit setup used for the on-state and transfer characteristics (see Fig. 6.). Unlike those simulations, where a fixed voltage step is applied, the off-state requires a variable voltage step. This allows the solver to use smaller steps near breakdown, where avalanche multiplication leads to sharp a current rise, while applying larger steps in low-field regions to reduce simulation time.

These conditions can be simulated using the curve tracer setup, where maximum voltage and current limits are defined as the breakdown criteria (see Fig. 7.). This avoids the need to specify a final voltage guess and prevents unnecessary calculations beyond the breakdown point. Furthermore, once the minimum current limit or voltage limit is reached, the biasing switches from a voltage source to a current source, which helps to capture the steep current rise near breakdown and makes the breakdown voltage easier to resolve.

tip

For more information see IV Curve Tracer.

Fig. 7. Curve tracer circuit setup and curve tracer properties window with the parameters used for these simulations.

note

Due to the very low leakage current values of SiC, the numerical precision of the solver needs to be set to quadruple in order to calculate the small values accurately.

7. Simulation Results

This section presents the simulation results obtained using the Aquarius TCAD Circuit and Device Simulator, focusing on the current–voltage characteristics in both the on‑ and off‑states. Key extracted parameters include threshold voltage, on‑resistance, and breakdown voltage.

7.1. On-state

7.1.1. Transfer Characteristics

The simulated transfer characteristics of model G1 at V_DS = 2 V, for temperatures of 300 K and 423 K, are shown in Fig. 8.

Based on the resulting channel doping concentration profile (see Fig. 4.), the threshold voltage is around 4 V at a drain current of $1\times10^{-3}$ A/cm² (T = 300 K). With increasing temperature (T = 423 K), the threshold voltage decreases due to the reduction in the Fermi potential caused by an increase in intrinsic carrier concentration with temperature. In addition, the transconductance (slope of the transfer curve) is reduced because of lower carrier mobility.

Fig. 8. Transfer characteristics of Model G1 at T = 300 and 423 K, with V_DS = 2 V.

7.1.2. Output Characteristics

The on-state drain current output characteristics (I_D – V_DS) for designs G1 and G2, evaluated at a gate-source voltages (V_GS) of 15 V and 20 V at T = 300 K, are illustrated in Fig. 9(a). Furthermore, Fig. 9(b) depicts the temperature dependence of the on-state curves for both designs at V_GS = 20V, comparing performance at T = 300 K and T = 423 K. The calculated specific on-resistance (R_on,sp) for designs G1 and G2 is summarised in Table 6.

Fig. 9(a). Comparison between design G1 and design G2 at V_GS = 15 V and 20 V (T = 300 K).

Fig. 9(b). Temperature-dependent characteristics for both designs at V_GS = 20 V, comparing performance at 300 K and 423 K.

Table 6. Comparison of specific on-resistance (R_on,sp) for designs G1 and G2

Design	Temp. (K)	VGS (V)	RON,SP (mΩ·cm²)
G1 (JFET width = 0.4µm)	300	15	1.81
		20	1.65
	423	15	2.86
		20	2.65
G2 (JFET width = 0.6µm)	300	15	1.26
		20	1.23
	423	15	2.02
		20	1.82

7.1.3. Channel Mobility

The channel mobility was estimated to be approximately 40 cm²/V·s at V_DS = 2 V and V_GS = 20 V (T = 300 K), which is slightly higher than the 15–30 cm²/V·s range typically reported in the literature for conventional planar SiC MOSFETs [1-3].

The simulated mobility distribution for model G1 is shown in Fig. 10. at T = 300 K. Taking a horizontal cut-line through the channel (15nm below the oxide / semiconductor interface), illustrated in Fig. 11., shows that with increasing temperature (T = 423 K), the channel mobility decreases from 40 cm²/V·s to 30 cm²/V·s, as expected due to enhanced carrier scattering at elevated temperatures.

note

The channel mobility parameter can be adjusted during the calibration to match the specific fabrication process and experimentally measured device data.

Fig. 10. Simulated mobility distribution throughout the device channel at T = 300 K (V_GS = 20 V, V_DS = 2 V).

Fig. 11. Horizontal mobility profiles extracted 15 nm below the oxide-semiconductor interface for T = 300 K and T = 423 K (V_GS = 20 V, V_DS = 2 V), illustrating the impact of thermal scattering on carrier transport.

7.1.4. Current Density

As reported in [1] and [3], a reduction in the JFET region width constricts the conduction path, thereby increasing the total specific on-resistance. This physical behaviour is verified by the current density distributions illustrated in Fig. 12(a) and (b).

Fig. 12(a). Simulated current density distribution for Model G1 at T = 300 K (V_GS = 20 V, V_DS = 2 V).

Fig 12(b). Simulated current density distribution for Model G2 at T = 300 K (V_GS = 20 V, V_DS = 2 V).

At V_GS = 20 V and T = 300 K, design G2 achieves a 25% reduction in R_ON,SP compared to design G1. At T = 423 K, the R_ON,SP reduction increases to 31%. However, the larger opening may lead to a higher EF reaching the gate oxide, as will be discussed in the next section.

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7.2. Off-state

7.2.1. Breakdown Voltage

Using the curve-tracer circuit setup (see Fig. 7.), the off-state blocking characteristics of G1 and G2 were simulated (T = 300 K), as shown in Fig. 13(a). The corresponding Electric Field (EF) distributions recorded at 700 V are shown in Fig. 13(b) and (c).

Fig. 13(a). Simulated breakdown characteristics (I_DS vs. V_DS) for model G1 and G2 at T = 300 K.

Fig. 13(b). Simulated electric field distribution at V_DS = 700V for Model G1.

Fig. 13(c). Simulated electric field distribution at V_DS = 700V for Model G2.

Both designs achieve a maximum blocking voltage of approximately 1200 V, with the G2 design showing a slight reduction of about 50 V due to the wider JFET opening, which increases the peak electric field (EF) in the p-body region and gate-oxide.

The vertical cut-lines through the points of maximum gate-oxide EF are shown in Fig. 14.

Fig. 14. Electric field profiles for Models G1 and G2 at V_DS = 700 V, extracted along vertical cut-lines through the device structure.
(Note: the gate oxide is on the far right of the graph at the top of the device)

At 700 V, the maximum gate-oxide electric field (EF) is 1.15 MV/cm for the G1 design and 1.8 MV/cm for G2, corresponding to a 56% increase. This highlights a trade-off between blocking capability, long-term gate-oxide reliability, and on-state performance. The full summary of both G1 and G2 design performance is summarised in Table 7.

Table 7: G1 and G2 Design Performance Summary (Vgs = 20V)

Design	VTH (V)	RON,SP (mΩ·cm2) (T = 300K)	RON,SP (mΩ·cm2) (T = 423K)	BV (V)	EFGOX (MV/cm)
G1	4	1.65	2.65	1200	1.15
G2	4	1.23	1.82	1150	1.8

8. Conclusion

This application note outlines the design and optimisation process of a 650 V MOSFET using the Aquarius TCAD tool. The study explores the trade-offs between on-state and off-state performance by varying the JFET width. A comprehensive analysis of the simulation results is presented, including 2D mobility maps, 2D current density, and electric field profiles. Additionally, the note details the meshing strategy, circuit configuration, and solver settings employed within Aquarius TCAD.

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9. References

[1] D. Kim, N. yun, S. Y. Jang, A. J. Morgan and W. Sung, "An Inclusive Structural Analysis on the Design of 1.2kV 4H-SiC Planar MOSFETs," in IEEE Journal of the Electron Devices Society, vol. 9, pp. 804-812, 2021, doi: 10.1109/JEDS.2021.3109605.

[2] H. Liu, J. Wei, Z. Wei, S. Liu, and L. Shi, “Experimental comparison of a new 1.2 kV 4H-SiC split-gate MOSFET with conventional SiC MOSFETs in terms of reliability robustness,” Electronics, vol. 12, no. 11, p. 2551, 2023, doi: 10.3390/electronics12112551.

[3] T. Liu, S. Zhu, A. Salemi, D. Sheridan, M. H. White, and A. K. Agarwal, “JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs,” Solid-State Electronics Letters, vol. 3, pp. 53–58, 2021, doi: 10.1016/j.ssel.2021.12.001.

10. Downloads

File	Description	Download
D1_SiC_Planar_MOSFET_G1.sdm	4H-SiC Planar MOSFET device model with geometry G1.	Download
D2_SiC_Planar_MOSFET_G2.sdm	4H-SiC Planar MOSFET device model with geometry G2.	Download
S1_On_State.sol	On-state solution file used for transfer and output simulations.	Download
S2_Off_State.sol	Off-state solution file used for breakdown simulations.	Download